Semiconductor wafers are typically composed of a substrate, on which a plurality of transistors has been formed. Integrated circuits are chemically and physically connected into a substrate by patterning regions in the substrate and layers on the substrate. Various metals, metal oxides, metal nitrides, metal alloys, and the like have been used to form electrical connections between interconnection levels and devices, including titanium, titanium nitride, aluminum-copper, aluminum-silicon, copper, tungsten, platinum, platinum-tungsten, platinum-tin, ruthenium, tantalum, tantalum nitride, and combinations thereof.
To produce an operable semiconductor wafer and to maximize the yield, performance, and reliability of the wafer, it is desirable to polish select surfaces of the wafer without adversely affecting underlying structures or topography. In fact, various problems in semiconductor fabrication can occur if the process steps are not performed on wafer surfaces that are adequately planarized.
Compositions and methods for planarizing or polishing the surface of substrates, such as semiconductors, are well known in the art. Polishing compositions (also known as polishing slurries) typically contain an abrasive material in an aqueous solution and are applied to a surface by contacting the surface with a polishing pad saturated with the slurry composition. Typical abrasive materials include silica (silicon dioxide), ceria (cerium oxide), alumina (aluminum oxide), zirconia (zirconium oxide), and tin oxide. U.S. Pat. No. 5,527,423, for example, describes a method for chemically-mechanically polishing a metal layer by contacting the surface with a polishing slurry comprising high purity fine metal oxide particles in an aqueous medium. Alternatively, the abrasive material may be incorporated into the polishing pad. U.S. Pat. No. 5,489,233 discloses the use of polishing pads having a surface texture or pattern, and U.S. Pat. No. 5,958,794 discloses a fixed abrasive polishing pad.
Conventional polishing systems and polishing methods typically are not entirely satisfactory at planarizing semiconductor wafers. In particular, polishing compositions and polishing pads can have less than desirable polishing rates, and their use in the chemical-mechanical polishing of semiconductor surfaces can result in poor surface quality. Because the performance of a semiconductor wafer is directly associated with the planarity of its surface, it is crucial to use a polishing composition and method that results in a high polishing efficiency, uniformity, and removal rate and leaves a high quality polish with minimal surface defects.
Chemical-mechanical polishing of tantalum-containing surfaces, such as tantalum removal in barrier film applications, typically utilize an oxidizing agent. Hydrogen peroxide is by far the most common oxidizing agent used in tantalum CMP. Hydrogen peroxide is a strong oxidizing agent that can react with other slurry components limiting pot-life stability of the polishing slurry composition. Electron transfer catalysts such as Fe, Os, or Ru cations can be added at low pH to act cooperatively with hydrogen peroxide to accelerate oxidation and removal of the metals present on the surface being polished. At elevated pH values, these metal electron transfer catalysts precipitate as oxide and hydroxide compounds, and lose their effectiveness as electron transfer catalysts. It is often also desirable to selectively oxidize tantalum in the presence of copper. Many common oxidizing agents are not selective between tantalum and copper.
There is an ongoing need for polishing composition and polishing methods that will exhibit desirable planarization efficiency and tantalum removal rate during the polishing and planarization of tantalum-containing substrates, and which do not rely on hydrogen peroxide for chemical removal of tantalum. The present invention provides such improved chemical-mechanical polishing compositions and methods. These and other advantages of the invention will be apparent from the description of the invention provided herein.